【正确答案】LIBRARY IEEE;
   USE IEEE.STD_LOGIC_1164.ALL;
   ENTITY mux4 IS
     PORT(d0，d1，d2，d3: IN STD_LOGIC;
         sel: IN STD LOGIC_VECTOR(1 DOWNT0 0);
         mux out: OUT STD_LOGIC);
   END mux4;
   ARCHITECTURE structurel OF mux4 IS
   BEGIN
   p0: PROCESS(d0，d1，d2，d3，sel)
   BEGIN
     CASE sel IS
       WHEN "00"=＞mux out＜=d0;
       WHEN "01"=＞mux out＜=d1;
       WHEN "10"=＞mux out＜=d2;
       WHEN "11"=＞mux out＜=d3;
       WHEN others=＞mux_out＜='X';
     END CASE;
   END PROCESS p0;
   END structurel;