摘要
SAR ADC每个转换周期的大部分时间被分配给ADC的量化操作,而只剩下少量的时间用来进行信号采样。在短时间内完成高精度的采样,需要前级电路具有更大驱动能力,同时要求ADC的采样开关具有更低的导通电阻。提出了一种交替采样结构,可以在不减少ADC量化时间的前提下,使得SAR ADC的采样时间等于量化时间,由此极大地降低ADC驱动电路的功耗。本文采用上述技术基于Fujitsu 55 nm工艺,实现了40 Msps 10 bit的异步SAR ADC,测试显示ADC有效位可达9.7 bit。
In conventional SAR ADC,most time of every conversion cycle is used for quantization,and only a little time is left for sampling,thus high driving capability buffer and low Ron sampling switch are indispensable.Otherwise,serious nonlinearity will generate.The proposed time-interleaved sampling architecture could extend the sampling time of SAR ADC to equal to quantization time without reducing the quantization time and conversion rate,thus greatly reducing the power consumption of ADC driver.This paper designed and implemented a 40 Msps 10 bit asynchronous SAR ADC based on Fujitsu 55 nm CMOS technology.The measurement results show the ENOB of the converter is 9.7 bit.
作者
葛彬杰
李琰
俞航
马四光
谢庆国
GE Binjie;LI Yan;YU Hang;MA Siguang;XIE Qingguo(College of Computer Science&Software Engineering,Shenzhen University,Shenzhen,Guangdong 518060,P.R.China;Department of Electronics and Computer Engineering SHENZHEN MCU-BIT University,Shenzhen,Guangdong 518172,P.R.China;Phsical Electronics Group of Jihua Laboratory,Foshan,Guangdong 528251,P.R.China;Department of Electronic Engineering and Information Science,University of Science and Tecnology of China,Hefei 230026,P.R.China;Department of Biomedical Engineering,Huazhong University of Science and Technology,Wuhan 430074,P.R.China)
出处
《微电子学》
CAS
北大核心
2023年第3期366-371,共6页
Microelectronics
基金
深圳市技术攻关重点项目(JSGG20191127151401743)
深圳市基础研究资助项目(JCYJ20190808165401679)
关键词
逐次逼近转换器
交替采样
混合切换
successive-approximation-register
time-interleaved sampling
hybrid switching
