摘要
针对图像传输领域在帧率和分辨率方面日益增长的需求,设计了用于图像采集的专用集成电路(ASIC)。电路为一种数模混合的14位复合结构ADC。采用FLASH辅助SAR的结构,通过FLASH ADC量化编码输入信号的高4位,并通过高4位编码辅助控制CDAC开关电容阵列,减少SAR ADC逐次比较的周期。为应对电容失配误差,设计了自校准电路及算法。基于SMIC130nm工艺,在电源电压3.3 V,数字逻辑电平电压1.2 V,转换速率2.6 MS/s的条件下进行了仿真,结果表明,该ADC的DNL为+1/-0.8LSB,INL为+1.2/-1LSB,SNDR为77.81 d B,ENOB为12.63bit,满足图像传输和图像采集领域高帧率、高分辨率的要求。
In consideration of the increasing demand of frame rate and resolution in the field of image transmission,an application-specific integrated circuit(ASIC)for image acquisition is designed.The circuit is a digital-analog hybrid14 bit composite structure ADC.It Uses the structure of flash assisted SAR.The high 4 bits of input signal are quantized and encoded by flash ADC,and the switch capacitor array of CDAC is controlled by high 4 bit encoding to reduce the period of SAR ADC successive comparison.In order to deal with the capacitor mismatch error,theself calibration circuit and algorithm are designed.Based on smic130 nm technology,the simulation is carried out under the condition of supply voltage of 3.3 V,digital logic level voltage of 1.2 V and conversion rate of 2.6 MS/s.The results show that the DNL of the ADC is+1/-0.8 LSB,theINL is+1.2/-1 LSB,the SNDR is 77.81 dB and the ENOB is 12.63 bit,which meets the requirements of high frame rate and high resolution in the field of image transmission and image acquisition.
作者
曾雪
郭函
陈功
ZENG Xue;GUO Han;CHEN Gong(College of Communication Engineering,Chengdu University of Information Technology,Chengdu 610225,China)
出处
《成都信息工程大学学报》
2020年第5期499-504,共6页
Journal of Chengdu University of Information Technology
基金
国家自然科学基金资助项目(61601065)
中国博士后基金资助项目(2017M612941)
