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JPEG2000中位平面编码的VLSI结构设计 被引量:1

VLSI Architecture of JPEG2000 Bit-Plane Coding
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摘要 位平面编码用于对量化的离散小波变换的码块数据进行编码.通过对位平面编码算法的分析和C语言验证,给出了位平面编码的四种基本编码操作和三个编码通道具体的VLSI结构实现.对位平面编码器的VLSI结构进行了仿真和综合,在图像验证系统上用逻辑分析仪实际测量的结果与仿真结果一致.该位平面编码器可在50MHz的主频下,完成32×32码块数据的编码.所设计的位平面编码器已经作为单独的IP核应用于目前正在开发的JPEG2000图像编码芯片中. Bit-plane coding is used to encode the code block of quantized discrete wavelet coefficients. The algorithm is studied and verified by C Language, then the VLSI architecture is proposed to implement the four basic coding operations and the three coding passes of bit-plane coding .The VLSI architecture is simulated and synthesized successfully. The practical results tested by logic analyzer under the image processing system shows that the architecture is correct. The 32×32 code block can be encoded efficient...
出处 《电子器件》 CAS 2007年第6期2229-2232,共4页 Chinese Journal of Electron Devices
关键词 JPEG2000 位平面编码 VLSI VERILOG HDL C语言 JPEG2000 Bit-Plane Coding VLSI Verilog HDL C Language
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