摘要
为提高卫星直接序列扩频系统的PN码捕获速度,提出了一种低硬件消耗的匹配滤波器设计。改进了转置型匹配滤波器结构,由两级时钟复用将匹配过程分为部分相关和全相关两部分,并用现场可编程逻辑阵列(FPGA)的片内RAM替代主要的寄存器消耗。实现了资源分配的优化,在商用FPGA的频率下可并行捕获长PN码,并降低了功耗,有一定的工程应用价值。
To fast the acquisition of PN code in direct sequence frequency-extended system in satellite,an improved matched filter with low hardware consumption was put forward in this paper.The architecture of the transposed filter designed was improved,in which the matched process was divided into partial and total correlation by a reusing of 2 level timing clock,and the major register was replaced by RAM in field programming gate array(FPGA) to realize the optimal of source distribution.The parallel acquisition for...
出处
《上海航天》
北大核心
2008年第4期61-64,共4页
Aerospace Shanghai
关键词
直接序列扩频系统
PN码
并行捕获
匹配滤波
时钟复用
现场可编程逻辑阵列
Direct sequence frequency-extended system
PN code
Parallel acquisition
Matched filter
Clock reuse
Field programming gate array
