摘要
根据CMMB中LDPC码校验矩阵的结构特点,提出了一种部分并行译码结构的实现方法,并在Altera的StratixII-EP2S180F1020C3型FPGA上实现了这种结构。该设计合理利用了LDPC校验矩阵的规律,使用了一种适当的存储器调用的控制策略,在几乎不增加硬件资源的情况下,实现了两种码率的复用。
According to the structure of LDPC code in China Mobile Multimedia Broadcasting(CMMB),a new architecture of a semi-parallel LDPC decoder is proposed in this paper and it is also implemented on FPGA(StratixII-EP2S180F1020C3).By fully utilizing the rule of LDPC check matrix,an appropriate method to control memories is proposed,which can reuse memories for two different code rates without increasing any memory usage.
出处
《电视技术》
北大核心
2009年第5期40-42,共3页
Video Engineering
