摘要
为了提高UART IP核的可重用性和灵活性,将其中波特率发生器模块设计成自适应的波特率发生器,同时采用异步FIFO作为UART与外部数据交换的缓冲器,实现处理器与UART接口的速度匹配.以IP核的参数化设计为基础进行Verilog HDL编码,在Modelsim SE 6.0上进行仿真验证,然后应用Synplicity公司的SynplifyPremier 9.6.2和Synopsys公司的DC 2008分别进行综合优化,并在FPGA上加以实现.结果显示,所提出的设计功能正确,可重用性强.
To improve the reusability and flexibility of the UART IP core,an auto-tuning baud rate generator is designed to replace the baud rate generator module.And for achieving the speed matching of the processor and UART interface,it takes asynchronous FIFOs as buffers to realize data exchange between UART and external devices.The proposed design,based on the parameterized design method of IP core,is described with Verilog-HDL.The whole design has been carried on the functional verification by Modelsim SE6.0.In the end,it is synthesized and optimized by Synplicity company's Synplify Premier9.6.2 and Synopsys company's DC 2008 respectively and is implemented by FPGA.The results show that the function of the proposed design is correct and has good reusability.
出处
《浙江大学学报（理学版）》
CAS
CSCD
2012年第5期535-540,共6页
Journal of Zhejiang University（Science Edition）
基金
国家自然科学基金资助项目(61041001)
浙江省自然科学基金资助项目(Z1090622)
浙江省教育厅科研基金资助项目(Y200906637)
