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VME总线桥控制器主模块和从模块的设计 被引量:9

Design of master and slave module in VMEbus bridge controller
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摘要 针对工控系统VME总线接口设计中成本高 ,灵活性差 ,自行设计也只是从模块简单应用的问题 ,介绍了在CPLD中实现VMEbus桥控制器过程中 ,功能完全的主模块和从模块的详细设计方法 ,并成功应用到SHARCDSP总线上。进行了逻辑原理设计 ,对各个部分的工作过程和功能进行了详细的分析。该方法可以实现完全的A32、A2 4、D32、D16、D8主 /从模块界面 ,并且可以选择以主处理器或DMA方式进行长度不限的块传输 ,设计灵活通用性强 ,性价比高。调试结果表明了该设计方法的实用性。 The requirement of VMEbus interface is often accounted in industrial control systems. The entire master and slave interface of VMEbus is often realized by using available IC of professional company, while the interface circuit designed by users themselves is currently only for simple application of slave module. In the realization of VMEbus bridge controller employing CPLD, the paper presents a method of entire master and slave function design at length, which is applied upon SHARC DSP bus successfully. Not only logic principles have been done, but also the work process and function of each part have been analyzed. It can act as complete A32, A24, D32, D16, D8 master and slave interface and can perform block transfer by means of DMA or master processor with no length limit. This design not only is flexible but also has high ratio of performance-to-price. Real results prove its practicability.
出处 《系统工程与电子技术》 EI CSCD 北大核心 2004年第7期954-957,969,共5页 Systems Engineering and Electronics
基金 总装备部预研基金 ( 5 14 0 70 2 0 2 0 1DZ0 117)资助课题
关键词 总线接口 VME总线 主模块 从模块 块传输 bus interface VMEbus master nodule slave module block transfer
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参考文献7

  • 1IEEE Standard for a Versatile Backplane bus: VME bus, 1987.
  • 2VMEbus Interface Handbook[M]. Cypress Semiconductor Data Book, 2001.
  • 3王宏伟,高梅国,韩月秋.基于VME总线SHARC并行处理系统的设计与实现[J].北京理工大学学报,2000,20(4):480-484. 被引量:7
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二级参考文献2

  • 1刘宝琴,AL TERA可编程逻辑器件及其应用,1995年
  • 2张澄波,综合孔径雷达原理、系统分析与应用,1989年

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引证文献9

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