摘要
设计并实现了一种适用于SBAS和Galileo卫星导航系统的(2,1,7)卷积码的Viterbi译码器.由于卫星导航系统中的数据率不高,采用串行结构实现Viterbi译码器,并且多通道复用同一译码器,以节省电路面积.此外,采用改进的加比选单元并通过寄存器交换法对幸存路径进行管理,以进一步优化电路结构.为了减少RAM的使用,利用同址更新技术将路径度量累加值和幸存路径存储至RAM.译码电路通过FPGA验证,采用SMIC65nm工艺库进行综合,该译码器逻辑电路的面积为4 738μm2.
AViterbi decoder is designed and implemented for(2,1,7)convolutional code in the SBAS and Galileo navigation systems.Since the data rate of the satellite navigation system is relatively low,the sequential architecture is applied and the Viterbi decoder is reused by all data channels in order to reduce area consumption.In addition,modified add-select-compare unit and register-exchange method have been used to further optimize the circuit.In order to reduce storage usage,RAM is accessed by in-place updating technology for path metric and survivor path.The decoder has been verified on the FPGA platform,and the synthesis result shows that the area of the logic circuit is 4 738μm2using 65 nm cell library.
出处
《微电子学与计算机》
CSCD
北大核心
2015年第1期60-63,67,共5页
Microelectronics & Computer
基金
国家自然科学基金项目(61376027
61221004)
