摘要
介绍了 3 DES加密算法的原理并详尽描述了该算法的 F PGA设计实现 ,设计中还采用了流水线技术来提高速度 ,添加了输入和输出接口的设计以增强应用的灵活性 ,各模块均用硬件描述语言 V HDL 实现 ,最终下载到 F PGA芯片Stratix中。
It introduces the principle of 3DES encryption algorithm and descripes the achievement of design on FPGA In the design,pipelining technology is used to improve its running speed,in order to enhance the flexibility,input and output interfaces are involved Besides,all the modules are programmed in hardware description language(VHDL) At last,download to FPGAStratix
出处
《现代电子技术》
2004年第21期55-57,共3页
Modern Electronics Technique
