摘要
提出了一种JPEG2000标准中MQ编码器的硬件设计方法,在采用并行结构的基础上,给出了一种高效的VLSI实现方案.使用的流水线结构使MQ编码器从总体结构上实现几个模块并行执行,用输出并行结构解决了同一时钟产生两个输出的问题,大大提高了输出模块的编码效率.仿真结果表明,该方案不仅能满足JEPG2000实时编码系统的要求,而且具有效率高和占用逻辑资源少的优点.
Hardware implementation of the MQ-coder for JPEC2000 standard is investigated. An efficient method for VLSI implementation described in VHDL is presented on the basis of making full use of parallel architecture. Pipe-line architecture used in this design makes several actions performed in parallel in general structure. Parallel output architecture solves the problem of generating tow bytes of compressed data in one clock, and at the same time greatly improves the efficiency of producing output data. The simulation results testify that this implementation can not only ensure the correctness, but meet the needs of the JPEC2000 coding system both in efficiency and resource occupancy.
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
2004年第5期714-718,共5页
Journal of Xidian University
基金
"十五"通信技术预研项目资助(41001030203)
863计划资助项目(2003AA1Z1310)
