摘要
通过一个设计实例,说明时序逻辑电路设计前的选型工作非常重要,如果选型不合适就可能得出错误结果.该实例被国内一些教材所引用,选用该例具有一定的意义.另外,还指出在状态图的化简过程中,对重复状态的认定应十分谨慎,绝不可把相似状态作为相同状态处理.
Through an example, the paper demonstrates the great importance of the selection of the model before sequential logic circuit is designed. As is shown in the paper, if wrong model is chosen, no correct result is likely to be produced. In addition, the recognition of the repetitive state requires great care, and under no circumstances should similar states be recognized as identical ones.
出处
《焦作工学院学报》
2004年第6期477-479,共3页
Journal of Jiaozuo Institute of Technology(Natural Science)
