摘要
介绍一种用于 1 0位分辨率 ,40MHz采样频率流水线结构模数转换器中的全差分采样 -保持电路设计。该采样 -保持电路是运用电容下极板采样技术设计的 ,不仅有效地避免了电荷注入效应引起的采样信号失真 ,而且消除了时钟馈通效应的不良影响 ;采用自举模拟开关来提高开关管的栅过驱动电压。采样 -保持电路中的运算放大器采用全差分结构 ,可以省略掉反馈电容。该电路基于 3V单电源供电的CMOS工艺 ,并利用HSPICE模拟软件 ,采用 0 .34μm工艺条件的BSIM 3 V3.1参数模型进行了模拟。
The design of a fully differential sampling-holding circuit used in 10-bit30M samples/s pipelined ADC is presented in this paper. The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through. The bootstrapped switch is used to improve the gate overdrive voltage. The fully differential operator can cancel the feedback capacitance. The circuit have been simulated in UMC 0.18um BSIM-V3.1 digital CMOS process by HSPICE. By theory analysis and simulation, the dc gain of the amplifier is 72.6dB, the gain-bandwidth is 500MHz, and this architecture can realize 9stage, 10 bit, 40Msamle/s pipelined A/D converter.
出处
《成都电子机械高等专科学校学报》
2004年第4期19-23,36,共6页
Journal of Chengdu Electromechanical College
关键词
全差分
采样-保持
CMOS
流水线
自举开关
Fully differential Sampling-holding CMOS Pipelined ADC Bootstrapped switch
