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一种32位全定制高速乘法器设计 被引量：2

Custom Design of 32-Bit Fast Multiplier
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摘要 对乘法器的多种实现方式作了综合比较 ,分析并实现了一种 32位全定制高速乘法器 ,该乘法器与 Synopsys DesignWare相应的乘法器相比速度快 14 %左右 .最后对 ASIC设计者选择不同用途的乘法器提供了相应的准则 . This paper compares different implementations of multipliers and analyzes the performance of full custom based ones. A full custom high performance 32 bit multiplier is also implemented, the speed of which is about 14% faster than the counterpart of Synopsys Design Ware. In the end guidelines on choosing multiplier for different applications are presented.
作者 王田 陈健 付宇卓
机构地区 上海交通大学芯片与系统研究中心
出处 《小型微型计算机系统》 CSCD 北大核心 2005年第2期307-309,共3页 Journal of Chinese Computer Systems
基金 国家"八六三"基金项目 (2 0 0 2 AA1Z)资助 .
关键词 乘法器 全定制 BOOTH编码 WALLACE TREE multiplier full-custom Booth encode wallace tree
分类号 TP331 [自动化与计算机技术—计算机系统结构]
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参考文献10

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同被引文献9

  • 1刘圆,黄晨灵,高佩君,闵昊.基于分段查找表的高速FIR滤波器的设计实现[J].微电子学,2006,36(5):674-678. 被引量：6
  • 2程佩青.数字信号处理教程[M].北京:清华大学出版社,2006.
  • 3Hu Aiping, Alldlalili A J. Comparison of constant coefficient multipliers for CSD and Booth recoding [A]. Microelectronics, The 14th International Conference on 2002 [C]. : 66 -69.
  • 4Lakshmanan, Othman M, Ali M A M. High performance parallel multiplier using Wallace-Booth algorithm [ A ]. Semiconductor Electronics, 21302. IEEE International Conference on 19 -21 Dec. 21302[ C] : 433 - 436.
  • 5Yoo Heejong, Anderson D V. Hardware-efficient distributed arithmetic architecture for high-order digital falters [A]. Acoustics, Speech, and Signal Processing, 2005. IEEE International Conference on Volume 5, 18-23 March 2005[C]. : 125-128.
  • 6Vojin G. Oklobdzija, David Villeger. Improving Multiplier Design by Using Improved Colum Compression Tree and Optimized Final Adder in CMOS Technology[ J ]. IEEE Transactions on very large sere integration systems, 1995, 2(3) :292-301.
  • 7]UweMeyer—baese.数字信号处理的FPGA实现[M].刘凌,胡永生,译.北京:清华大学出版社,2006.
  • 8Cheng C,Parhik K. Low- cost Parallel FIR Filter Structures with 2 - stage Parallelism[J]. IEEE Transactions on Circuits and Systems, 2007(54) : 280 - 290.
  • 9Chen Xiaoping,Qu Bo,Lu Gang. An Application of Immune Algorithm in FIR Filter Deslgn[J]. Proceedings of the 2003 International Conference on Neural Networks and Signal Processing, Nanjing, China, 2003( 1 ) : 473 - 475.

引证文献2

二级引证文献5

小型微型计算机系统
2005年 第2期

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