A buffer planning algorithm for chip-level floorplanning
A buffer planning algorithm for chip-level floorplanning
摘要
This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. In this paper, we proposed a buffer planning algorithm based on dead space redistribution to make good use of dead-spaces for buffer insertion. Associated with circuit blocks under topological representations, the dead space can be redistributed by moving freely some circuit blocks within their rooms in the placement. The total area and the topology of the placement keep unchanged while doing the dead space redistribution. The number of nets satisfying the delay constraint can be increased by redistributing the dead space all over the placement, which has been demonstrated by the experimental results. The increment of the number of nets that meet delay constraint is 9% on an average.
二级参考文献18
-
1[11]Ma Yuchun, Hong Xianlong, Dong Sheqin et al., VLSI floorplanning with fixed topology, Microelectronics(in Chinese), 2000, 30: 22-24.
-
2[12]Young, E Y., Wong, D. F., Yang, H. H., Slicing floorplans with preplaced modules, in Proc. IEEE Int. Conf.Computer-Aided Design, 1998, 252-258.
-
3[13]Murata Hiroshi, Fujiyoshi Kunihiro, Kaneko Mineo, VLSI/PCB placement with obstacles based on sequence pair, in IEEE Trans. on Computer Aided Design, 1998, 17( 1): 60-67.
-
4[14]Young, F. Y., Wong, D. F., Slicing floorplans with range constraint, in Proc. Intl. Symp. on Physical Design(ISPD99) (ed. IEEE), 1999, 97-102.
-
5[15]Young, F. Y., Wong, D. F., Yang, H. H., Slicing floorplans with boundary constraints, in IEEE Trans. on Computer Aided Design, 1999, 18(9): 1385-1389.
-
6[16]Kang, M., Dai, W. M., General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure, in Proceedings of IEEE Asia and South Pacific Design Automation Conference(ASP-DAC97) (ed. IEEE), 1997, 265-270.
-
7[17]Huang, G., Hong, X. L., Qiao, C. G. et al., A timing driven block placer based on sequence pair model, in Proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC99) (ed. IEEE), 1999,249-252.
-
8[18]Nagao, A., Shirakawa, I., Kambe, T., A layout approach to monolithic microwave, IEEE Trans. on Computer Aided Design, 1996, 17(12): 1262-1272.
-
9[1]Lauther, U., A min-cut placement algorithm for general cell assemblies based on a graph representation, in Proceedings of 16th ACM/IEEE Design Automation Conference (DAC79) (ed. ACM, IEEE), 1979, 1-10.
-
10[2]Dai, W. M., Eschermann, B., Kuh, E. S. et al., Hierarchical placement and floorplanning in BEAR, in IEEE Trans. on Computer Aided Design, vol. CAD-8, 1989, ( 12): 1335- 1349.
-
1Onkyo（安桥）TX-NR1009[J].家庭影院技术,2011(8):4-4.
-
2潘涵,杨张帆,宋东安.阵元平面布置端射特性的仿真分析[J].舰船科学技术,2012,34(6):67-69. 被引量：1
-
3徐超.中国联通定制多普达钻石2[J].通信世界,2009(36).
-
4频率合成器、功率合成器、均衡器、衰减器[J].电子科技文摘,2002,0(4):28-29.
-
5CAI Yici HONG Xianlong ZHANG Yiqian.An Efficient Algorithm for Construction under Fixed Buffered Routing Tree Buffer Locations with Accurate Delay Models[J].Chinese Journal of Electronics,2006,15(3):393-398.
-
6任苙萍.嵌入式微处理器平台 打造SoC硅晶时代[J].电子与电脑,2005,5(6):54-57.
-
7尚清涛.全球频率监管热点问题[J].现代电信科技,2010(2):47-53.
-
8周骥伟,戎世怡,刘凌志,戎蒙恬.高性能IC版图综合中的互连线时延估计模型[J].微电子学,2003,33(1):5-8.
-
9Xu, Penggen, Lu, Shu, Xu, Ying.Conversion Technique of Vector Wave Functions:Formulas and Applications[J].Journal of Systems Engineering and Electronics,1997,8(3):6-15.
-
10赵爱萍.iWorld、iTV与“iWords”[J].科技英语学习,2009(10):50-52.
