摘要
介绍了电子侦察用数字信道化接收机的设计思想,提出了FPGA具体实现结构。重点论述了采用多相滤波器实现信道化的原理和使用FPGA实现的方法,并给出了仿真结果图。为了达到实时处理的效果,FIR的FPGA实现采用查表结构,FFT的FPGA采用流水线结构和并行结构。这两种实现方式都极大地提高了运算速度,使数字信道化接收机的实时处理成为可能。此外,文中还对频率估计、检测和判决逻辑部分进行了相应的介绍。
A design idea of the digital channelized receiver for electronic surveillance is introduced in this paper and the implementation structure of the FPGA is presented. The emphasis is put on the principle of adopting the polyphase filter and the FPGA to realize channelization. The simulation result in this regard is also given. In order to get to the effect of real-time processing, the structure of table look-up and the structrue of pipelining and parallelling are respectively employed in the FPGAs of FIR and FFT. These two ways greatly improve the operating rate and make the real-time processing of the digital channelized receiver possible. Besides,the frequency estimation and detection and the logic decision are introduced in the paper.
出处
《雷达与对抗》
2005年第1期50-54,共5页
Radar & ECM
