摘要
向集成电路版图中填充金属哑元(dummy)可减少化学 机械抛光所产生的介质厚度差异,同时它也给传统的寄生电容提取工具带来性能上的巨大挑战.本文基于虚拟多介质加速的直接边界元法,提出一种有效处理含有哑元填充互连结构的三维电容提取算法.通过采用悬浮(floating)边界条件和有效的方程形成和求解方法,该算法在保持高精度的同时,速度比Raphael快几千倍、比文[5 ]中方法快十多倍.利用本文算法,还对含哑元结构进行了一系列试验,分析其对互连电容的影响,有助于集成电路的优化设计.
The insertion of dummy metals is necessary to reduce the pattern-dependent variations of the dielectric thickness in the chemical-mechanical polishing (CMP) process. This makes conventional tools of capacitance extraction exhibit prohibitive calculation time. This paper presents an efficient method for 3-D capacitance extraction with taking the floating dummies into account. Based on the QMM-accelerated BEM, our method inherits high computational speed while considering the floating conditions and using a new preconditioner. While preserving high accuracy, our method shows an excellent speed with l000x speed-up over Raphael, about 10x speed-up over the method in Ref.[5]. Finally, we carried out a series of experiments on cases which contain floating dummy-fills. The influence of dummy-filling on interconnect capacitance is analyzed and conclusions are drawn to benefit the design of high performance integrated circuits.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2005年第4期667-670,共4页
Acta Electronica Sinica
基金
国家自然科学基金(No90407004)
国家863高技术研究发展计划(No2004AA1Z1050)
关键词
寄生电容提取
悬浮金属哑元
化学
机械抛光
边界元法
虚拟多介质
Boundary element method
Calculations
Chemical mechanical polishing
Dielectric materials
Extraction
Integrated circuits
Metals
Three dimensional
