摘要
现代计算机的基本框架仍是以冯·诺伊曼结构为基础,以中央控制单元和存储指令/数据的存储器之间的通信为支撑的。同步动态随机存储器(即SDRAM)与静态RAM相比具有容量大,成本低的优势;与传统异步DRAM相比其速度更快,所以得到了越来越广泛的应用。因此以简化主机对SDRAM访问为主要任务的SDRAM控制器的设计就变得更加重要。论文提出了一种基于状态机的SDRAM控制器的设计思路与实现,并通过了FPGA验证,完全达到系统的功能和速度要求。
The architecture of modern computers is still based on Von-Neumann idea,which heavily relies on the communication between the CPU and the RAM,which stores the instructions and data.Retaining the preponderance over SRAM while still much faster than the traditional asynchronous DRAM,SDRAM is put to use in more and more applications.For this reason,the SDRAM controller designed chiefly to simplify the low level transactions of SDRAM is becoming even important.This paper presents a design and implementation method based on FSM,which has been verified through FPGA verification and meets all functional and speed requirements of the system.
出处
《计算机工程与应用》
CSCD
北大核心
2005年第17期110-112,132,共4页
Computer Engineering and Applications
关键词
SDRAM
状态机
刷新
SDRAM,Finite State Machine(FSM),refresh
