摘要
提出了普通阵列乘法电路的改进结构和含流水线的串并乘法电路(SPM)结构。后者比基于Booth算法的n位并行乘法电路更节省资源消耗,由O(n2)降低到O(n),同时相比于n位普通移位乘法器,运算时间复杂度由的O(n2)降低到O(n),且其串行输出特性更适合应用于大数乘法电路。
Two circuit structures which are the optimized multiplier with full-adder array and the serial-parallel multiplier with pipeline inside are put forward. The latter reduces the consumption of resource from O(n2) to O(n) in contrast to the n-bit multiplier based on Booth algorithm. Meanwhile, comparing to the shift-add multiplier, it speeds up the computation from the time complexity O(n2) down to O(n). Further more, its serial output characteristic makes it more suitable for large number multiplier.
出处
《半导体技术》
CAS
CSCD
北大核心
2005年第8期65-68,共4页
Semiconductor Technology
基金
2003年教育部科学技术研究重点项目(03130)
