摘要
高速特发引擎的设计是T比特路由器设计中的关键和难点,本文围绕传输带宽需求、查表时间需求和包头处理时间需求以及器件水平等方面对基于FPGA实现的10Gbps高速转发引擎进行了详细的分析,讨论了高速转发引擎各功能模块的设计可行性,并给出了一种可行的实现方案。
The 10Gbps forwarding engine is one of the most challenge task in terabit router design. In order to design a 10Gbps forwarding engine with FPGA, the transmission bandwidth requirement between each elements in FPGA, IP look-up time, header processing cycle number and the up-to-date development of FPGA are all analyzed in detail. So the number of fiber to provide enough transmission bandwidth is calculated, a fast IP look-up scheme is presented and a header processing module of parallel and pipeline structure is provided. Finally the implementing scheme of the 10Gbps forwarding engine is proposed.
出处
《计算机科学》
CSCD
北大核心
2005年第6期14-17,共4页
Computer Science
基金
国家十五‘863’信息技术领域重大专项课师(NO 2003AA103510)
