摘要
集成电路芯片的规模不断增大,功能越来越复杂,设计验证工作量也越来越大,成为整个设计周期的“瓶颈”。文章针对同步数字体系(SDH)宽带交换芯片设计中的功能验证,设计了初步的SDH验证平台,提出了具有一定通用性的SDH芯片的功能验证方案和实现方法,包括分层的描述和验证方法,一系列标准测试数据和自动观测模拟结果的若干加速C程序。该平台已用于40Gbit/s交换芯片的功能验证,加速了验证过程,取得了满意的效果。
The function verification of integrated circuits has become the bottleneck of the design cycle because of the increasing scale and the complexity of chips. In order to verify the design of ASIC chip in the field of SDH, this paper presents a primary verification platform, which includes various layers for specifying test benches and a library of standard data, as well as some C programs for comparing simulation dada with expected data. The platform has been use for verifying the design of 40 Gbit/s switch chip with satisfactory results.
出处
《光通信研究》
北大核心
2005年第4期61-63,共3页
Study on Optical Communications
基金
国家"十五"科技攻关基金资助项目(2002BA106B)
国家自然科学基金资助项目(90207015)
