摘要
为了提高六自由度强震观测系统的集成度以及可靠性,并降低它的系统成本,用现场可编程门阵列(FPGA)芯片取代六自由度强震观测系统内的∑-Δ型A/D转换器组件中的有限冲击响应(FIR)抽取滤波器芯片CS5322。根据FPGA芯片的特点,FIR数字抽取滤波器采用分布式算法来实现,这种方法实现的基础是查找表。同时,采用部分表结构实现的分布式算法大大降低了对FPGA芯片内部系统资源的占用。用这种方法,分别设计了芯片CS5322中三级FIR抽取滤波器,并且,在1片低成本EP1C12芯片中集成了8片CS5322的功能,完成了设计目标。
In order to improve the integration level, reliability and reduce the total cost of a 6 degree-freedom strong ground motion observation system,its FIR decimation filter chip CS5322 of ∑-△ type A/D converter chip set in the system are replaced by FPGA. According to the character of FPGA, the FIR digital decimation filter is implemented via using distribution algorithms which are based on the technique of looking up table. In the same time, the usage of the FPGA embedded resources is reduced greatly because of using partial LUT configuration to implement the distribution algorithms. 3 FIR decimation filters in CS5322 are designed respectively by using this method. Equivalent functions of 8 CS5322 chips are integrated into only one low cost EP1 C12 chip, and the design target is achieved.
出处
《传感器技术》
CSCD
北大核心
2005年第8期28-30,33,共4页
Journal of Transducer Technology
基金
国家自然科学基金资助项目(50378086)
地震科学联合基金资助项目(104139)
关键词
有限冲击响应抽取滤波器
现场可编程门阵列
分布式算法
查找表
finite impulse response（FIR） decimation filter
field programmable gate array （FPGA）
distribution algorithms
look up table
