摘要
为了提高SoC内部总线的性能,优化总线架构。文章提出了一种新颖的LotteryBus总线机制。通过将其与静态优先级及时分复用总线进行比较,介绍了它的特点及其仲裁机制。并且设计和实现了一个4-Masters的Lot-teryBus用于龙芯SoC内部高速总线的改进,功能仿真和FPGA验证证明这一总线机制的可行性和正确性。
This paper presents LotteryBus, a novel communication architecture for System on a Chip （SoC） designs Through comparing LotteryBus with static priority based shared bus and time division multiplexed access based architecture, we describe features and arbiter mechanism of it. Moreover, we design a 4-Masters LotteryBus for the improvement of Godson SoC Processor Local Bus, and it has good performance proved function simulation and FPGA verification.
出处
《微电子学与计算机》
CSCD
北大核心
2005年第7期76-78,共3页
Microelectronics & Computer
基金
国家自然科学基金项目(60373043)
国家863高计划项目(2002AA1Z1040)
