摘要
本文介绍了高速数字流水Ｖｉｔｅｒｂｉ译码器的ＶＬＳＩ设计。在符号４值系统的基础上，给出Ｖｉｔｅｒｂｉ算法的新的功能分解公式，并介绍了用于译码器实现的两个重要的快速运算部件ＡＤＤ和ＭＡＸ的原理及其现场可编程（序）门阵列（ＦＰＧＡ）实现。文中详细讨论了译码器的ＶＬＳＩ结构、设计和性能分析。本文给出的Ｖｉｔｅｒｂｉ译码器可塑性强，并具有高度的并行性和很高的数据吞吐率。
A new VLSI design of digital pipelined Viterbi decoder is presented in this paper. Based on the sign-digit system, a new decomposition formula of Viterbi algorithm is described. The architecture of Viterbi decoder is also discussed. Two key components of Viterbi decoder are implemented by using field-programmable gate arrays (FPGA's). Our Viterbi decoder has high degree of parallelism and flexibility.
出处
《通信学报》
EI
CSCD
北大核心
1995年第3期50-55,共6页
Journal on Communications
关键词
VLSI
集成电路
设计
译码器
Viterbi decoder, digital pipelined, systolic array, FPGA's,VLSI design
