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A CMOS Fully Integrated Frequency Synthesizer with Stability Compensation 被引量:1

CMOS集成频率综合器的稳定性补偿(英文)
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摘要 A complete closed-loop third order s-domain model is analyzed for a frequency synthesizer. Based on the model and root-locus technique, the procedure for parameters design is described, and the relationship between the process,voltage,and temperature variation of parameters and the loop stability is quantitatively analyzed. A variation margin is proposed for stability compensation. Furthermore,a simple adjustable current cell in the charge pump is proposed for additional stability compensation and a novel VCO with linear gain is adopted to limit the total variation. A fully integrated frequency synthesizer from 1 to 1.05GHz with 250kHz channel resolution is implemented to verify the methods. 通过分析频率综合器的完整三阶闭环s域模型,同时采用根轨迹分析技术,定量分析了工艺、电压和温度引起的环路参数变化对频率综合器稳定性的影响,并提出变化裕量的概念来进行稳定性分析和参数设计.为了获得更加稳定的系统,在电荷泵中设计了结构简单的电流单元用于补偿额外的参数变化,并采用线性压控增益的VCO来减小参数的变化.最后设计了一个分辨率为250kHz,频率范围为1~1.05GHz的集成频率综合器来验证上述的分析和设计方法.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第8期1524-1531,共8页 半导体学报(英文版)
基金 上海市科学技术委员会2003年度集成电路设计科技专项(批准号:037062019) 上海应用材料研究与发展基金(批准号:0425)资助项目~~
关键词 frequency synthesizer closed-loop third-order s-domain loop parameters PVT variation STABILITY variation margin 频率综合器 闭环三阶s域 环路参数 PVT变化 稳定性 变化裕量
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参考文献14

  • 1Wilson W B,Moon U K,Lakshmikumar K R,et al. A CMOS self-calibrating frequency synthesizer. IEEE J Solid-State Circuits,2000,35(10) :1437
  • 2Rategh H R, Samavati H, Lee T H. A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver. IEEE J Solid-State Circuits,2000,35(5) :780
  • 3Colleran D M, Portmann C, Hassibi A, et al. Optimization of phase-locked loop circuits via geometric programming. Custom Integrated Circuits Conference, 2005: 377
  • 4Craninckx J,Steyaert M. A fully integrated CMOS DCS-1800frequency synthesizer. IEEE J Solid-State Circuits, 1998, 35(12) :2054
  • 5Terrovitis M,Mack M,Singh K,et al. A 3. 2 to 4GHz 0.25μm CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN.IEEE International Solid-State Circuits Conference, 2004: 98
  • 6Zhao Hui, Ren Junyan, Zhang Qianling. A 900MHz CMOSPLL/frequency synthesizer initialization circuit. Chinese Journal of Semiconductors,2003,24(12) :1244
  • 7Larsson P. A 2-1500-MHz CMOS clock recovery PLL with low-Vdd capability. IEEE J Solid-State Circuits, 1999, 34 (12):1951
  • 8Gardner F M. Charge-pump phase-lock loops. IEEE Trans Commun, 1980,28(11) :1849
  • 9Hanumolu P K, Casper B, Mooney R, et al. Analysis of charge-pump phase-locked loops. IEEE Trans Circuits & Systems-I:Regular Papers,2004,51(9) :1665
  • 10Hein J P,Scott J W. z-domain model for discrete-time PLL's.IEEE Trans Circuits and Systems,1988,35(11) :1393

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  • 2池保勇,石秉学,王志华.射频锁相环型频率合成器的CMOS实现[J].电子学报,2004,32(11):1761-1765. 被引量:6
  • 3唐长文,何捷,菅洪彦,闵昊.An Accurate 1.08GHz CMOS LC Voltage-Controlled Oscillator[J].Journal of Semiconductors,2005,26(5):867-872. 被引量:1
  • 4宁彦卿,王志华,陈弘毅.利用Van der Pol方程分析MOS LC差分振荡器[J].微电子学,2006,36(1):4-8. 被引量:2
  • 5宁彦卿,王志华,陈弘毅.An Ultra Wideband VHF CMOS LC VCO[J].Journal of Semiconductors,2006,27(1):14-18. 被引量:1
  • 6BHATTACHARJEE J,MUKHERJEE D,GEBARA E,et al.A 5.8 GHz fully integrated low power low phase noise CMOS LC VCO for WLAN applications[C]∥IEEE Microwave Symposium,Digest.Seattle,USA,2002:585-588.
  • 7PAVLOVIC N,GOSSELIN J,MISTRY K,et al.A 10GHz frequency synthesizer for 802.11a in 0.18μm CMOS[C]∥The 30th European Solid-State Circuits Conference.Leuven,Belgium,2004:367-370.
  • 8LI Z B,KENNETH K O.A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator[J].IEEE Journal of Solid-State Circuits,2005,40(66):1296-1302.
  • 9CHU Y K,CHUANG H R.A fully integrated 5.8GHz U-NII band 0.18μm CMOS VCO[J].Microwave and Wireless Components Letters,2003,13(7):287-289.
  • 10WU S M,LIU R Y,CHEN W L.A 5.8 GHz high efficient,low power,low phase noise CMOS VCO for IEEE 802.11a[C]∥The 3rd IEEE Int Workshop on SOC for Real-Time Applications.Calgary,Alberta,Canada,2003:94-97.

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