摘要
本文提出了一个AES加密算法的高速低功耗ASIC设计方案,使用Synopsys设计流程和VeriSilicon0.18μmCMOS工艺,实现了最高工作频率410MHz,数据吞吐率5.23Gbps,功耗为58mW。采用改进算法(T盒算法),将轮变换操作中的不同步骤合并为一组表的查询,有效降低了关键时序路径的传输延迟,并通过动态功耗管理和门控时钟等低功耗设计方法有效地降低了功耗。
This paper implements a high-speed, low-power AES ASIC. In 0.18μm CMOS technology of VeriSilicon and with Synopsys design flow, the design runs at 410MHz resulting in a throughput of 5.23 Gbps while consuming 58mW. The T-Box algorithm, which merges the S-Box and another primitive function （MixColumns） into a single function, is used for reducing the delay of critical data path. And several low-power techniques, such as power management and clock gating, are applied for power optimization.
出处
《微计算机信息》
北大核心
2005年第09X期8-10,共3页
Control & Automation
基金
中国科学院知识创新重大项目资助编号:KGCX-SW-15
