摘要
对AMBA-总线进行了简要介绍,并给出一SOC芯片中DDR SDRAM控制器的AHB总线接口的具体实现和验证方法。该设计采用Verilog进行RTL级实现,并在FPGA系统中得到验证。在基于0.18um工艺的库中综合频率达到160MHz,满足设计要求。
This article simply describes the characteristics of AMBA on chip bus. Then, an implementation of the AHB slave interface to a DDR SDRAM Controller is presented. The RTL level of this design is implemented in Verilog HDL, and verified in FPC-A. The frequency of this design can reach 160Mhz with 0.18m process library and meet our requirements.
出处
《计算机与数字工程》
2005年第10期130-132,136,共4页
Computer & Digital Engineering
