摘要
优化FPGA设计,须对工作速度与使用面积综合评价,并在二者中找到平衡点。速度优化通过流水线设计、寄存器配平或关键路径实现。面积优化通过资源共享技术实现,并使用同步电路提高设计可靠性。
In order to optimize the FPGA design, firstly, the work speed and usable floor space is estimated, and the balance spot between them was found. The work speed is optimized through the pipelining design, register matching or key path. The usable floor space is optimized by source sharing technique, and the reliability of design is improved by using synchronic circuit.
出处
《兵工自动化》
2005年第5期102-102,106,共2页
Ordnance Industry Automation
