摘要
FPGA是一种新型的高密度大容量的PLD。RS码是目前应用最广泛的纠错编码之一。本设计并不讨论RS码的算法,RS编/译码部分直接利用Altera公司的ReedSolomonCompiler生成。针对FPGAAPEX20K系列器件,实现RS编/译码应用。并在此基础上,通过比较运用FIFO宏模块前后的编译报告,发现运用FIFO宏模块能够使设计所占用的资源大大减少,说明FPGA内部逻辑优化的重要性。
FPGA is a new type of PLD,which has high- density and large capacity. RS is widely used now as error correcting coding. This paper dose not discuss algorithm of RS. RS encoder or decoder is generated directly by Reed - Solomon Compiler. This pager realizes the application of RS encoder or decoder on FPGA APEX20K. Comparing with the compile report of before using FIFO megafunction with the one of after,we can easily find that FIFO megafunction help to reduce the design capability. It is very important that optimizing FPGA internal logic.
出处
《现代电子技术》
2006年第3期125-127,共3页
Modern Electronics Technique
