摘要
重点讨论了应用于功率集成电路的高压电源和地之间的一种采用动态检测电路的ESD保护电路,介绍了他的电路结构和工作原理,利用HSpice软件对其在ESD脉冲和正常工作2种情况下的功能进行了仿真,并模拟了保护电路中各器件的尺寸对电路性能的影响。仿真结果证明这种保护电路能满足ESD保护的要求,实际流水结果通过了4 kV HBM测试。
In this paper, a high voltage VDD -to -VSS ESD protection circuit using transistor delay and the considerations of design in power IC are proposed. The good performance of the ESD protection circuit under ESD pulse and in work condition is proved by HSpice,and the influence of the devices＇ sizes is analyzed. Finally, this ESD protection circuit has been fabricated and verified：the HBM ESD level is over 4 kV
出处
《现代电子技术》
2006年第4期141-144,共4页
Modern Electronics Technique
