摘要
文中分析高速背板设计中所面临的问题,给出相应的设计准则。在此基础上,以所设计的交换机背板为例给出利用时钟缓冲分配芯片实现的时钟信号分配电路的实例。最后,说明针对时钟电路的设计所采取的具体措施。结果表明,利用上述设计方案可以使整个系统在90MHz的时钟频率下稳定工作,实现高达2·88Gbps的数据传输速率。
In this paper, the problems for high speed backplane design are analyzed and also given out the corresponding design principles. Based on the switch backplane we implemented, clock distribution circuit by using a clock buffer distribution chip has been illustrated. Finally, it presents the specific methods adopted for designing the clock circuit. The results shows that by means of the scheme discussed above, the whole system can work stably at 90MHz clock frequency and realize a dada transmission rate up to 2. 88Gbps.
出处
《电子测量技术》
2006年第1期10-11,共2页
Electronic Measurement Technology
关键词
时钟信号
印刷电路板
特性阻抗
clock signal print circuit board （PCB） phase 10ck loop （PLL）
