摘要
论文介绍一种使用PCI宏核逻辑进行高效PCI接口设计的方法。该方法将PCI接口逻辑和PCI用户逻辑集成在一片FPGA里,可以对整个逻辑进行仿真调试,大大缩短了开发周期,提高了系统集成度和性能。文章重点介绍了PCI接口逻辑的结构原理,分析了时序设计的要点,并给出了一种典型应用的软硬件设计方案和仿真结果。
The paper presents a method of high efficiency PCI bus design using PCI macro core logic.This method integrates the PCI interface logic and PCI user＇s logic in one FPGA chip,and then we can simulate and test the whole logic from the top layer,which shorten the development period and improve the system integration degree and capability effectively.The paper describes the structure and principle of PCI interface logic emphatically and analyzes the key of the timing design.Finally the software and hardware design scheme and simulation result of a typical application are given to demonstrate the effectiveness of our method.
出处
《计算机工程与应用》
CSCD
北大核心
2006年第9期80-82,共3页
Computer Engineering and Applications
