摘要
针对数字电路设计中面积和速度相互矛盾的问题,提出了AES算法的一种优化处理方法,将加密和解密共用一个存储器,并以此为基础针对密钥分组为128位的情况,对硬件结构进行了优化处理,使密钥扩展与加/解密模块共用4个替换盒,充分利用了硬件资源,达到较高的速度/面积比,由此设计出了适合IC卡的AES协处理器,并用Xilinx公司的集成开发软件XilinixISE6.0对该设计进行功能仿真、布局布线后仿真验证,结果证明本设计优化设计方案的可行性达到了IC卡对AES协处理器的要求.
Considering the problem of the chip area and the speed during the design of digital circuit, this lmtXw put forward an optimization method of the AES algorithm. In this paper, the operation of encryption and decryption used the same memorizer. Aiming at the encryption which grouped for 128 bit, we also gave an optimization rnethods of its structure, in which the extension of the key and the blocker of the encryption and decryption used the same four changing boxes, thin fully using the hardware resource. In thisway, we attained a high ratioof the speed to the area. Based on this method, we designed a AES processor which could could the demand of IC card. Later, the design was simulated on the operation flat of the XilinixISE6.0, which was impoldered by the corporation of Xilinx. From the simulation result, we could see that the speed of encryption and decryption satisfied the requirement of IC card for the AES processor, which showed that the design was feasible.
出处
《湖南大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2006年第2期66-69,共4页
Journal of Hunan University:Natural Sciences
基金
湖南省自然科学基金资助项目(03JJY3097)
