摘要
针对如何用复杂可编程逻辑器件实现4DPSK信号的解调,提出了一种基于CPLD的4DPSK信号解调器设计方案.先将4DPSK信号通过双门限比较器等进行二值数字化,再用VHDL语言设计实现对此数字化后的二值逻辑信号进行延迟、相移、逻辑运算和识别等处理,实现对4DPSK信号的解调.此设计方案减小了硬件实现的复杂度,迎合了可编程逻辑器件CPLD对数字逻辑信号进行处理的特点,并给出了用可编程逻辑器件CPLD实现部分的仿真波形.
This article presents a design scheme of 2-digitization 4DPSK demodulator, which aim at how to implement 4DPSK signal demodulate with CPLD. Firstly the 4DPSK signal becomes 2-digitization through double-gateway comparer, then the latter signal passes through delay, phase shift, Logic operation, recognition process and so on using VHDL to demodulate the 4DPSK signal. This scheme reduces the complexity of hardware, caters to the transaction feature of digital logic signal of CPLD, presents simulation waveforms also.
出处
《河北大学学报（自然科学版）》
CAS
北大核心
2006年第3期310-314,共5页
Journal of Hebei University(Natural Science Edition)
