摘要
对数字下变频各个模块的构成及原理进行了研究,提出了一种基于高效抽取滤波器的实现方案,用查表法产生数字混频所需的高采样率的数字本振信号,用梳状滤波器和半带滤波器级联实现数字下变频的抽取和滤波.方案中多处使用了查表法,它相对于传统方法有节省资源,速度快,易于实现的优点.设计中调用了ALTREA参数化模块库中的资源,充分利用了芯片的硬件资源,从而提高了运算速度.还给出了半带滤波器的一个设计实例.该方案已通过FPGA验证.
The paper carried out a research on the structure and the theory of DDC＇s each module, and put forward a scheme of realizing DDC with high efficiency decimation filters. Look-up table was used to realize the digital high sampling rate local oscillator, and CIC （cascade ontegrator comb） filters and HB （Half-Banol） filters were used to realize the decimation of DDC. Look-up table was used for many times in the scheme. Compared with traditional methods, Look-up table has the advantage of resource saving, high speed and the easy realization. The design used library of parameterized modules of ALTREA, which made the most of the chip＇s hardware resource, thereby improved the speed. A design instance of HB filter was also given. It has been demonstrated with FPGA.
出处
《华中科技大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2006年第6期14-17,共4页
Journal of Huazhong University of Science and Technology(Natural Science Edition)
关键词
数字下变频
现场可编程门阵列
数字本振
梳状滤波器
半带滤波器
查表法
digital down converter（DDC）
field programmable gate anry（FPGA）
digital local oscillator
cascade integrator comb filter
half-band filter
look-up table
