摘要
提出了一种高速V iterbi译码器的FPGA实现方案。该译码器采用全并行结构的加比选模块和寄存器交换法以提高速度,并且利用大数判决准则和对译码器各个部分的优化设计,减少了硬件消耗。译码器的最高输出数据速率可以达到90 Mbps。译码器的性能仿真和FPGA实现验证了该方案的可行性。
The FPGA implementation of a high - speed Viterbi decoder is presented. In order to improve the speed of the decoder, an all - parallel structure of the add - compare - select unit and the register exchange algorithm are adopted. The hardware resources are reduced by means of the majority rule and some optimizations . The maximal data output speed of this decoder is up to 90Mbps. Simulation and FPGA implementation show that this design is feasible.
出处
《电讯技术》
2006年第3期37-41,共5页
Telecommunication Engineering
基金
总参通信部"十五"预研项目(11001030501)
