摘要
介绍了基于FPGA芯片的星载合成孔径雷达实时成像处理器中方位压缩处理器的设计与实现。该处理器可根据参数实时生成匹配滤波参考函数,用频域方法实现雷达回波的方位向压缩,并输出实图像。处理器与主控间采用ISA总线接口。介绍了方位压缩的原理和功能,详细描述了处理器硬件开发和FPGA设计。测试结果表明,该处理器可以实现星载条件下雷达数据的方位压缩。
Azimuth compressor is an essential part of the real-time processor of the synthetic aperture radar （SAR）. The design and the implementation of the azimuth compressor based on FPGAs for space-borne SAR are introduced. The compressor generates a real-time match filtering function from the parameters of the space-borne SAR and implements the azimuth compression of the signals in the frequency domain, then exports the real image as a result. The in- terface between the compressor and the master computer is applied to the ISA connector. The principle and the function of the azimuth compression are presented, and the hardware development and the software design of the compressor are presented. Experimental results show that the compressor accomplishes azimuth compression under space condition.
出处
《数据采集与处理》
CSCD
北大核心
2006年第2期154-158,共5页
Journal of Data Acquisition and Processing
关键词
合成孔径雷达
方位压缩处理器
现场可编程门阵列
ISA接口
synthetic aperture radar（SAR）
azimuth compressor
field programmable gate array （FPGA）
industry standard architecture （ISA） connector
