摘要
详细讨论了在MAX plus II开发平台下使用VHDL硬件描述语言设计现场可编程门阵列(FP-GA)时常见的三个问题:等占空比分频电路、延时任意量的延时电路、双向电路。
Three familiar problems of using VHDL hardware description language to design FPGA under the MAX plusⅡ development platform are discussed in detail,the grade duty ratio frequency dividing circuit ,the time delay circuit, the bilateral circuit.
出处
《国外电子元器件》
2006年第7期30-33,共4页
International Electronic Elements
关键词
FPGA
VHDL
分频电路
延时电路
双向电路
FPGA
VHDL
frequency dividing circuit
time delay circuit
bilateral circuit
