摘要
文章针对在语音、视频等多媒体信号处理中出现的可变速率信号,设计了一种新型的高速低功耗可重构流水线乘法器电路,该电路可通过改变流水级数使运算频率与待处理的信号频率相匹配,明显地降低了功耗、提高了效率。并在0.25μmCMOS工艺条件下对该电路性能进行了仿真、分析、比较。在保证最大频率为1.04GHz的高运算速度情况下,最多可节约电路功耗36%。
This paper bring forward a new high speed and lower power wasting re-configurable pipeline multiplier, for the alterable velocity signal process in sound and video. The circuit change the frequency with different pipeline stage, it improve the efficiency and reduce the power waste . The circuit was simulation under 0.25μm CMOS process. The circuit reduce the power waste by 36 percent effectively for the alterable velocity of signal process and remain the high speed of 1.04GHz by control the pipeline number.
出处
《微电子学与计算机》
CSCD
北大核心
2006年第8期14-16,共3页
Microelectronics & Computer
基金
国家自然科学基金项目(60476046)
国家部委基金项目(51408010304DZ0140)
关键词
可重构
高速
低功耗
乘法器
流水线
Re-configurable, High speed, Low-power waste, Multiplier, Pipeline
