摘要
用于JPEG2000静止图像压缩编码FPGA实现的图像验证系统。整个系统平台是由一个并口CMOS电脑眼、两个FPGA芯片、UART接口以及外部缓存组成。为了对搭建的平台进行验证,将并口电脑眼采集的图像数据存储在外部SRAM中,然后通过UART接口传送到PC机中,并通过PC机端的串口接收程序把采集的图像显示出来。完成了图像采集模块和UART接口模块的verilog HDL模型描述,通过了仿真和逻辑综合,并下载到FPGA芯片中,编写了串口接收程序,成功地实现了系统的联机调试。
： This paper presents an image processing system which is suitable for JPEG2000 FPGA implementation. The system contains a CMOS camera, two FPGA chips, an UART interface and some external memories. In order to verify the system, images captured by the CMOS camera are stored in external memories and then transmitted to PC through the UART interface, the receiver program then captures the data and displays the images on CRT. The Verilog HDL modules of image capture and the UART interface are programmed, simulated and synthesized to FPGA. The receiver program is designed and the image processing system is implemented successfully.
出处
《电子器件》
CAS
2006年第3期825-828,共4页
Chinese Journal of Electron Devices
