摘要
在简单分析SOVA译码算法的基础上,对SOVA子译码器IP核的设计进行了整体分析;从硬件实现的角度,对译码算法的特征进行了理论分析,得到了对称状态节点的软信息具有确定关联的结论;并据此优化了硬件设计,极大地减少了存储资源的占用。同时,采用其他两种减少存储空间的优化设计方案和流水线策略,进一步减少了SOVA子译码器的功耗。对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明,文章提出的优化方案可行、有效,极大地降低了硬件资源占用和功耗。
Base on SOVA algorithm, an SOVA sub-decoder IP core is designed and the function of each module is described. Furthermore, an associated theory about extrinsic information, which was used to optimize the hardware implementation, is analyzed. Other two optimizations to reduce the memory unit were also adopted in the key module design to limit the power dissipation. And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.
出处
《微电子学》
CAS
CSCD
北大核心
2006年第5期642-645,650,共5页
Microelectronics
基金
广州市科技计划攻关重点项目资助(2004Z3-D0321)
