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嵌入式处理器中降低Cache缺失代价设计方法研究 被引量:3

Research on Reducing Cache Miss Penalty of Embedded Processor
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摘要 以龙芯1号处理器为研究对象,探讨了嵌入式处理器中降低Cache缺失代价的设计方法.通过分析处理器的结构特征,本文实现了在关键字优先基础上一次缺失下命中的非阻塞数据Cache,可以将处理器平均性能提高3.9%.同时利用局部性原理,在关键字优先非阻塞数据Cache的基础上,本文提出了一种类非阻塞的指令Cache设计方法,可以降低指令Cache的缺失代价,以较小的实现代价进一步将处理器平均性能提高7.7%.通过本文的工作,可以同时降低指令Cache和数据Cache的缺失代价,处理器的平均性能提高了11.6%. With godson-1 processor as the research prototype,a real chip developed by ICT-CAS, this paper is focused on the design methodology of reducing cache miss penalty of embedded processor. By analyzing the processor architecture ,a hit-under- one-miss non-blocking data cache based on critical-word-prior technique is implemented,and the processor performance is improved 3.9 %. At the same time a hit-under-one-miss non-blocking-alike instruction cache technique is presented to reduce the instruction cache miss penalty,and the processor performance is improved 7.7%. Both data cache and instruction cache miss penalty is reduced significantly by the methodology presented in this paper at the same time, and total 11.6% processor performance improvement is achieved.
出处 《小型微型计算机系统》 CSCD 北大核心 2006年第11期2077-2081,共5页 Journal of Chinese Computer Systems
基金 中国科学院知识创新工程项目高性能通用CPU芯片研制(KGCX2-109) 中国科学院知识创新重大项目高性能通用CPU芯片研制(KGCX1-SW-09)
关键词 嵌入式处理器 CACHE 缺失代价 embedded processor cache miss penalty
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参考文献9

  • 1Uhilg R A,Mudge T N.Trace-driven memory simulation:a survey[J].ACM Computer Survey,1997,29(2):128-170.
  • 2John L.Hennessy,David A.Patterson.Computer architecture:a quantitative approach(second edition)[M].China Machine Press,2002:309-321.
  • 3Przybylski S,Horowitz M,Hennessy J.Performance tradeoffs in cache design[C].Computer Architecture,1988.Conference Proceedings.15th Annual International Symposium on 30 May-2 June 1988,(s):290-298.
  • 4Chu P P,Gottipati R.Write buffer design for on-chip cache[C].Computer Design:VLSI in Computers and Processors,1994.ICCD '94.Proceedings.,IEEE International Conference on 10-12 Oct.1994,(s):311-316.
  • 5Memik G,Reinman G,Mangione-Smith W H.Reducing energy and delay using efficient victim caches[C].Low Power Electronics and Design,2003.ISLPED '03.Proceedings of the 2003 International Symposium on 25-27 Aug.2003,(s):262-265.
  • 6Drach,N.Seznec,A.MIDEE:smoothing branch and instruction cache miss penalties on deep pipelines microarchitecture[C].1993.Proceedings of the 26th Annual International Symposium on1-3 Dec.1993,(s):193-201.
  • 7Yeager K C.The mips R10000 superscalar microprocessor micro[J].IEEE,Volume 16,Issue 2,April 1996,(s):28-41.
  • 8Power4 System Microarchitecture WhitePaper[EB/OL].http://www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power4.html,2005.
  • 9Kessler R E.the alpha 21264 microprocessor[J].Micro,IEEE.Volume March-April 1999,19,(2):24-36.

同被引文献29

  • 1陈书明,李振涛,万江华,胡定磊,郭阳,汪东,扈啸,孙书为.“银河飞腾”高性能数字信号处理器研究进展[J].计算机研究与发展,2006,43(6):993-1000. 被引量:29
  • 2黄海林,范东睿,许彤,朱鹏飞,郑保建,曹非,陈亮.嵌入式处理器在片调试功能的设计与实现[J].计算机辅助设计与图形学学报,2006,18(7):1005-1010. 被引量:9
  • 3Henessy J L, Patterson D A. Computer Architecture: A Quantitative Approach[M]. Third Edition.北京:电子工业出版社,2004:257-258.
  • 4Sule A M. Design of Pipeline Fast Fourier Transform Processors Using 3 Dimensional Integrated Circuit Technology[ D ]. PHD Thesis, NCSU, 2007.
  • 5Henessy J L, Patterson D A. Computer Architecture: A Quantitative Approach[M]. Fourth Edition.北京:电子工业出版社,2007:412-413.
  • 6Guo Y, Chheda S, Koren I, et al. Energy-aware Data Prefetching for General-purpose Programs[C]//Processings of Power-aware Computer Systems, IEEE CS Press, Portland, USA, 2004:78-94.
  • 7Jouppi N P. Improving Direct-mapped Cache Performance by the Addition of a Small Fully-associative Cache and Prefetch Buffer[C]//Proc. of 17^th Annual Int'l Symposium on Computer Architecture, 1990:364 - 373.
  • 8郇丹丹,李祖松,胡伟武,刘志勇.结合访存失效队列状态的预取策略[J].计算机学报,2007,30(7):1104-1114. 被引量:3
  • 9Shen Haihua,Zhang Heng,Xu Tong.Verification of a configurable processor core for system-on-a-chip designs[C] //Proceedings of the 6th International Conference on ASIC,Shanghai,2005:891-894
  • 10Albin Ken.Nuts and bolts of core and SoC verification[C] //Proceedings of the 38th ACM/IEEE Design Automation Conference,Las Vegas,2001:249-252

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