摘要
设计了一种实现算术编码的集成电路IP核,可用于下一代静止图像压缩标准JPEG2000编码系统中。采取易于硬件实现的二进制算术编码算法,分析了该IP核的各个模块和时序,在ModelSim软件中进行了功能仿真,在QuartusⅡ软件中完成了综合以及布局布线,并在自行设计的一块FPGA的PCI开发板上进行了验证和性能分析。实验结果表明,对相同的图像进行编码,该IP核的处理时间仅为软件处理时间的41%。该文的研究对于JPEG2000在实际中的应用有着重要的意义。
An circuit IP perforating arithmetic coding is designed to he implemented in JPEG2000, which is the newly developed still image processing standard. A binary arithmetic coding algorithm, which is easy to be implemented in hardware is used, The module structure and time sequence of the IP core are described. Function verification is carried out with Model-sire, synthesis and routing are conducted with Quartus II. The design is verified on a PCI-based FPGA development board. With the same inputs, the outputs show that the hardware arithmetic encoder designed by this paper can perform its computation in approximately 40% of the time taken by the arithmetic coding module in the Jasper software. The research of the thesis makes it possible for JPEG2000 to be used in reality.
出处
《计算机工程》
EI
CAS
CSCD
北大核心
2006年第21期255-257,共3页
Computer Engineering
基金
上海工程技术大学青年科学基金资助项目(2004Q17)
