摘要
随着集成电路规模的不断增大,芯片的可测性设计正变得越来越重要。研究了目前较常用的边界扫描测试技术的原理、结构,并给出了边界扫描技术的应用。重点研究了基于边界扫描的外测试方式,即电路板上芯片间连线的固定故障、开路和短路故障的测试;利用硬件描述语言Verilog设计出TAP控制器,得到TAP状态机的仿真结果。
With the increase of the scale of integraled circuits, design for testability of IC＇s is becoming more and more important. In this paper, the theory and architecture of boundary scan test technology is introduced and researched,then its application is given. Outside test method is researched based on boundary scan technology mostly, namely design for test of stuck at fault,open circuit and short circuit between chips on a PCB（Printed Circuit Board）. Finally, TAP controller is schemed out by HDL Verilog language, and simulating result of TAP State Machine is gained.
出处
《重庆邮电学院学报（自然科学版）》
2006年第6期686-688,723,共4页
Journal of Chongqing University of Posts and Telecommunications(Natural Sciences Edition)
基金
重庆市高校中青年骨干教师资助项目(D2003-10)
重庆邮电学院自然科学基金资助项目
关键词
边界扫描
数字集成电路
可测性设计
boundary scan
digital integrated circuits
design for testability
