摘要
介绍了JPEG2000编解码流程以及JPEG2000算术编码的原理。针对传统算术解码器过慢的情况,提出了一种动态的流水线算术解码器结构,给出了相应的硬件实现的框图,该结构通过FPGA验证。采用了TSMC0.25μm工艺,进行了ASIC的实现。
This paper introduces JPEG2000 encode and decode flow, and also the principle of JPEG2000 arithmetic coding. Traditional arithmetic decoder is very slow that may be the bottleneck of the JPEG2000 system. To solve this problem, a pipeline arithmetic decoder is present here, together with the hardware chart. The arithmetic decoder is verified with FPGA and is implemented in TSMC 0.25 μm technology.
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
2006年第6期920-923,共4页
Journal of University of Electronic Science and Technology of China
基金
国家863计划资助项目(2002AAIZ1450)
