摘要
首先建立缺陷空间分布和粒径分布的模型，并讨论了缺陷通过版图产生电路错误的过程，给出了ＩＣ功能成品率模拟器ＸＤ－ＹＥＳ的实现。用ＸＤ－ＹＥＳ对微电子测试图和实际ＩＣ的功能成品率模拟和分析表明，其结果与实际符合很好，从而表明ＸＤ－ＹＥＳ的可行性和实用性。
t first of this paper,the models of defect spatial distribution and size distribution on silicon wafer have been built, and the procedures of producing circuitlayout faults by defects are discussed. The method and procedure of realizing iCfunctional yield simulator XD-YES are given. Simulation of functional yield of bothmicroelectronics test pattern and practical iC has shown that the calculating resultsagree with the practical ones. The feasibility and utility of XD-YES are demonstrated.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
1996年第4期365-371,共7页
Research & Progress of SSE
基金
863高科技项目
国家博士点基金
关键词
功能成品率
缺陷分布
集成电路
Functional Yield Defect Distribution Circuit Faults
