摘要
在CCD内部结构的基础上,分析了CCD的动态功耗和静态功耗两部分.静态功耗是CCD片上输出放大器所消耗的功率;动态功耗是由于CCD驱动时钟对时钟电极的串联等效电容或极间电容进行充放电,充放电电流流过多晶硅电极电阻或串联等效电阻引起功率耗散.分别给出了二者的估算方法,其中动态功耗的估算方法有集总模型估算法、分布式模型估算法及PSpice仿真估算法三种.结合具体项目,在对CCD47-20的工作模式和工作时序分析的基础上,采用集总模型估算法对其功耗进行了估算,并通过实验估测验证了估算方法的有效性.
Power dissipation in CCD, which is composed of static power dissipation and dynamic power dissipation, is analyzed based on the clock register structure in CCD. Static power is dissipated in the on-chip output amplifier. Dynamic power dissipation, however,is the energy dissipation caused by the charged or discharged current flowing through the resistance of polysilicon clock line and the series equivalent resistance of the clock electrode when the clock pulse is applied to the device. The methods to estimate these two power dissipations are proposed in this paper. As for estimating the dynamic power dissipation, lumped model, distributed model and PSpice simulating are presented in detail. The methods are applied in calculating the power dissipation in CCD47-20 after analyzing its work mode and work timing. In the end, the validity of the calculating methods is verified by comparing the estimated value with the measured value.
出处
《光子学报》
EI
CAS
CSCD
北大核心
2007年第1期174-179,共6页
Acta Photonica Sinica
