摘要
通过分析异步FIFO的结构和关键技术,以减少电路中亚稳态出现概率为主要目的,提出了一种有效实现异步FIFO的设计新方法。结合FPGA对设计的异步FIFO进行了验证并针对两种FIFO模型做了性能比较,结果表明该设计大大提高了工作频率和资源利用率。
This paper analyses the structure and key technique of asynchronous FIFO. In order to reduce the probability of metastability in the circuit, the paper presents a new method which implement asynchronous FIFO effectively. Aim at the asynchronous FIFO, this article also describes the werification experiment of the design and makes a perform compare between the two FIFO model. The result of measurement indicates that this design improves the frequency and the utilization of resources greatly.
出处
《微电子学与计算机》
CSCD
北大核心
2007年第3期210-213,216,共5页
Microelectronics & Computer
基金
西北工业大学研究生创新种子基金(Z200646)
