摘要
通过一个0.18μm CMOS工艺、低功耗Sigma-Delta ADC调制器(SDM)部分的设计研究,提出了一种深亚微米下混合信号处理系统的设计方法,论述了从系统级行为验证到电路级验证的设计流程,与传统流程相比,在行为级验证中采用了SIMULINK建模方法,在电路级的验证中,提出了从宏模型验证到晶体管级细电路验证这样一种新颖的设计方案,其中所提出的宏模型以6.5%的仿真时间获得97.5%的仿真精度,晶体管级电路以此指标设计,确保其一次验证通过,提高了系统设计效率。
Through the design verification of a 0.18 μm CMOS low power Sigma-Delta ADC modulator, a new deep-submicron mixed-signal system design method is presented in this paper. Compared to traditional design flow, the SIMULINK model is adopted in the systematical behavioural verification,and the SPICE macro model to transistor circuit design as the circuit level verification method is created. The macro model gets 97.5 % precision but only cost 6.5 % simulation time of the fine circuit level. The transistor circuits can be designed according to the macromodel specification and verified only in one time, resulting in improvement of the system design efficiency.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2007年第1期63-68,共6页
Research & Progress of SSE
基金
国家863项目(2003AA1Z1120)资助
