摘要
如何有效地利用处理器消耗的能量而得到尽可能高的性能成为了目前体系结构研究的热点,在研究中,结构级的功耗评估工具无疑具有重要的作用.在现有的结构级功耗模拟器中,往往只考虑了动态电路以及全定制实现方法下的功耗刻画,而忽略了以静态电路和标准单元设计为主的ASIC设计方法对处理器功耗带来的影响.由此,结合一款高性能、低功耗通用处理器——龙芯2号的具体实现,对其设计特点和功耗特性进行分析,实现了以龙芯2号处理器为基本研究对象的结构级功耗评估方法.该评估方法充分考虑了CMOS静态电路的结构级功耗刻画方法,因此更加适合目前以ASIC设计方法为主的高性能处理器结构的功耗评估.该结构级功耗评估方法与RTL级的功耗评估方法相比,具有速度快和灵活性好的优点.在2.4GHz的IntelXeon上,该功耗评估方法的速度约为300K/s,是RTL级的评估方法的5000倍,而且误差很小.
Now the research of computer architecture focuses on how to utilize the energy of CPU to attain high performance as much as possible. Obviously the architecture-level power estimation tool is important. Existing architecture-level power simulators only focus on full-custom dynamic circuits modeling, but ignores the power modeling of ASIC designs which are mainly composed of static circuits or standard cell libraries. So this paper is concerned with the implementation of a high performance and low power general purpose CPU, the Godson-2 processor, and analyzes the power characteristics of the CPU, and implements an architecture-level power estimation methodology which aims at the Godson-2 processor. This methodology takes the power modeling methodology of CMOS static circuits into account carefully, so it is better for the estimation of current high performance CPU architecture which is designed with ASIC methodology. Compared with the RTL power estimating method, this methodology has high speed and high flexibility and the accuracy is also very good. On the platform of Intel Xeon 2.4GHz, the speed of this methodology is about 300K instructions per second, which is 5000 times that of the RTL power estimating method with only little error penalty.
出处
《计算机研究与发展》
EI
CSCD
北大核心
2007年第5期782-789,共8页
Journal of Computer Research and Development
基金
国家"九七三"重点基础研究发展规划基金项目(2005CB321600)
国家自然科学基金项目(60673146)
国家杰出青年基金项目(60325205)
国家"八六三"高技术研究发展计划基金项目(2005AA110010
2005AA119020)
中国科学院计算技术研究所知识创新基金项目(20066012
20056240)~~
